The present invention relates to solid-state imaging apparatus in which it is feasible to read outputs of the light receiving pixels in an optionally selected region of the light receiving portion thereof.
One for example as disclosed in Japanese Patent Application Laid-Open Hei-4-277985 is known as a solid-state imaging apparatus having the capability of reading the light receiving pixels in an optionally selected region of its light receiving portion such that a shift register serving as a scanning means for time-serially reading the outputs of light receiving pixels is divided into a plurality of blocks so as to read a region of the light receiving portion corresponding to the divided blocks. With this read method, however, the unit of repetition by the shift register is a divided block so that there is a possibility of the quality of signals being changed at the boundary of one block with another. Further, since selection of the region to be read out becomes possible only with taking each block previously set at the time of manufacture of the solid-state imaging apparatus as a unit, the reading of the signals from an optionally selected region cannot be effected.
A shift register for solving such problem has been proposed by the present applicant in Japanese Patent Application Laid-Open Hei-6-350933. The construction of the shift register is shown in FIG. 1. A description will be first given with respect to the construction of such shift register. FIG. 1 includes: 1, a shift register unit having serially connected first clocked inverter 1-1 and second clocked inverter 1-2; 2, a storing switch; 3, a transmitting switch; 4, a storing section formed by serially connecting a first inverter 4-1 and second inverter 4-2.
An output node of the first clocked inverter 1-1 is connected to one end of the storing switch 2 and of the transmitting switch 3. Further, the other end of the storing switch 2 is connected to an input of the first inverter 4-1 of the storing section 4, and an output of the second inverter 4-2 of the storing section 4 is connected to the other end of the transmitting switch 3. Numeral 6 denotes a unit stage of the shift register. While a 7-stage shift register is shown in FIG. 1, many more stages are provided in a shift register to be actually used in solid-state imaging apparatus.
The first clocked inverter 1-1 becomes active when a drive clock Φ 2 is at H level, and the second clocked inverter 1-2 becomes active when a drive clock Φ 1 is at H level. It should be noted that /Φ 1, /Φ 2 indicate inverted clocks of drive clocks Φ 1, Φ 2. A start pulse Φ ST is inputted to an input of the first-stage shift register unit 1. Further, the storing switch 2 becomes conductive when a memory pulse Φ M is at H level, and the transmitting switch 3 becomes conductive when a transmitting pulse Φ T is at H level. It should be noted that /Φ M, /Φ T denotes inverted pulses of the memory pulse Φ M and transmitting pulse Φ T.
An operation of thus constructed shift register will now be described by way of the timing chart shown in FIG. 2. First in a prescanning (scan location setting period) before a main scanning, H level is inputted to the start pulse Φ ST at time T1, and it is shifted according to clocks Φ 1, Φ 2 within the shift register. To start the main scanning from the third-stage shift register unit, then, memory pulse Φ M is driven to H level at time T2, so as to store the level status at this time of node SR0.5, SR1.5, SR2.5, . . . SR6.5 within each shift register unit 1 into the storing section 4. In other words, the input node of the storing section 4 of the first, second, fourth, fifth, sixth, seventh unit blocks is caused to store H level, and the input node of the storing section 4 of the third unit block is caused to store L level.
Subsequently, by driving the transmitting pulse Φ T to H level at time T3, the level stored at time T2 is transmitted to the node SR0.5, SR1.5, SR2.5, . . . SR6.5 within each shift register unit 1. Since, at that point in time, clock Φ 1 is at H level, inverted outputs of the nodes SR0.5, SR1.5, SR2.5, . . . SR6.5 are outputted to the nodes SR1.0, SR2.0, SR3.0, . . . SR7.0 within each shift register unit 1, respectively. Thereafter, since these outputs are shifted in accordance with clocks Φ 1, Φ 2 within the shift register, the scanning of the shift register is to be started from node SR3.0 of the third-stage shift register unit. At time T4, by bringing the transmitting pulse Φ T to H level to transmit information in the storing section 4 again, the scanning of the shift register is started from SR3.0 in a similar manner as that followed time T3. Accordingly, in the main scanning period starting from time T3, the scanning of the shift register is started from node SR3.0 based on the transmitting of the information stored at the storing section 4.